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Principal Engineer
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Job Summary:-_
Seeking highly motivated, energetic, team-oriented Individual Contributor driving roadmaps for IP / SS domain including complete IP portfolio, going deeper into logic design and architecting and developing Complex IPs / Subsystems solutions. Working closely with experienced and motivated team of Global experts in Systems, SoC Design functions to address the design/architectural challenges in the context of the complex IP and overall System level solutions. Work through a wide spectrum of skill from developing High level Specifications to actual design Implementation.
Key Responsibilities:
- Own and drive Roadmaps for complete IP / Subsystem domains portfolio within global R&D team.
- Perform benchmarks against other industry players and ensure differentiating features for our customer with high level of innovation.
- Architect and Design complex IP and Subsystems across a range of protocols required for Automotive Self Driving Vehicles (ADAS) both Vision and Radar, In-Vehicle networks, Gateway Systems, Fail Safe Subsystems (ASIL-D) etc.
- Own and Lead IP / Subsystem from Concept till IP Design and Development achieving final design performance in integrated system within aggressive, market driven schedules.
- Ensure quality adherence during all stages of the IP development cycle and carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure 'Zero Defect' designs and drive and mentor teams towards that.
Key Skills
- Self starter with 10-14 years of hands-on experience to Architect and Design complex IP design / Sub-system with minimal supervision.
- Custom Processor Designs with key DSP functions like those needed for Vision and Radar processing.
- Experience in High Speed Serial protocols and associated high speed challenges on controller and PHY for PCIe, Ethernet & MIPI CSI2.
- Understanding of key External Memory interface protocols including DDR4 / LPDDR4, QuadSPI Flash interfaces.
- Experience in microcontroller architecture, Cache, protocols like AHB/AMBA,AXI.
- Extensive hands on knowledge of HDLs (Verilog/VHDL), Scripting languages (Perl, Tcl), C/C++ for hardware modeling.
- Understanding of end to end IP development flow including complex CDC, RDC constructs, IP Synthesis, DFT ATPG coverage.
- Have worked on Testbench and Testplan development closely with the verification team.
- Hands on work on pre silicon validation using FPGA/Emulation Board would be a significant added advantage.
Key Soft Skills
- Proficient skills in both written and verbal communication. Can articulate well.
- Has a sense of Ownership and engages everyone with Trust and Respect.
- Should demonstrate Emotional Intelligence and Leadership values with ability to work well as a part of team both local and remote or multisite
