DFT Engineer

Greetings from ACL Digital!We’re expanding our Semiconductor Design Center of Excellence and looking for highly skilled DFT (Design for Test) Engineers to join our dynamic team in Noida and Bangalore locations.If you’re passionate about cutting-edge SoC and ASIC design and have strong expertise in BIST, ATPG, Scan, and advanced DFT methodologies, this is...

Purpose of the Role:The Design for Testability (DFT) engineering organization at L&T Semiconductor Technologies (LTSCT) pioneers innovative methods and technologies in the areas of DFT architecture, verification, and post-silicon bring-up of state-of-the-art semiconductor chips, such as System on a Chip (SoCs), developed using the latest semiconductor...

DFT EngineerLocation : Bangalore Notice Period:30 daysJob Description: We are looking for a skilledDFT Engineerwith 3–5 years of experience in ASIC design and verification with a strong focus on Design-for-Test methodologies. You will be responsible for implementing and verifying DFT architectures to ensure high test coverage and manufacturability. Key...

Role: DFT Engineer (Design for Testability)Location: NoidaExperience: 7–10 yearsBudget: Open / As per company standardsQualification: BE/ME/B.Tech/M.Tech from a reputed instituteWhat You’ll Work On:Implementation and verification of scan architectures, JTAG (Joint Test Action Group), boundary scan, Memory BIST, LBIST, and ATPG (Automatic Test Pattern...

Role: DFT Lead Experience:10+ years Location: Bangalore Salary: Can be discussedJob Description We are looking for an energetic, passionate and process oriented DFT Leads who has extensive experience in planning, implementation and verification of DFT features for multiple SoC. Direct Responsibilities of the role, but not limited to, working on various...

Role: DFT Engineer Experience: 4 to 12 Years Location: BengaluruJob Description:Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes...

Purpose:The Design for Testability (DFT) engineering organization at L&T Semiconductor Technologies (LTSCT) pioneers innovative methods and technologies in the areas of DFT architecture, verification, and post-silicon bring-up of state-of-the-art semiconductor chips, such as System on a Chip (SoCs), developed using the latest semiconductor technology...

GLOBAL MNC:Location: Greater Bengaluru Area Our main business focuses on automotive microcontrollers and SoCs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips. It will continue to integrate the latest electronic and electrical architecture (E/EA) designs from...

Position: DFT Engineers Experience: 3+ relevant experience. Location - IndiaTo Be Successful In This Role You WillSeeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Design for Test skills and Tools .Technical Skillset RequiredGood knowledge in DFT...

Role: DFT EngineerExperience: 4 to 12 YearsLocation: BengaluruJob Description:- Will be responsible for Designing and Implementing DFT techniques. - Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. - Test Modes...