PCIe Design Verification Lead
5 months ago
Hi All,
Greetings from Wipro...
We are actively looking for Sr. Design Verification Lead/ Manager with PCIe Protocol Experience:
10-12+ years of experience in IP/Subsystem level Verification.
Good hands-on experience in verifying PCIe protocol (Gen4/Gen5/Gen6).
Good knowledge on PCIe transaction layer, routing, reset flows etc.
Good experience with AXI protocol, NOC subsystem verification.
Good SV-UVM knowledge with hands-on experience in testbench development.
Good debugging skills.
Knowledge on performance verification is a plus.
Be able to lead a team of 8-10 members with technical ownership of the project.
Locations: Hyd, Delhi (NCR), Chennai, Bangalore, Cochin, Ahmedabad, Pune, Mumbai, Etc).
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PCIe Design Verification Lead
5 months ago
Bengaluru, India Wipro Full timeHi All,Greetings from Wipro...!We are actively looking for Sr. Design Verification Lead/ Manager with PCIe Protocol Experience: 10-12+ years of experience in IP/Subsystem level Verification.Good hands-on experience in verifying PCIe protocol (Gen4/Gen5/Gen6).Good knowledge on PCIe transaction layer, routing, reset flows etc.Good experience with AXI protocol,...
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PCIe Design Verification Lead
5 months ago
Bengaluru, India Wipro Full timeHi All, Greetings from Wipro...! We are actively looking for Sr. Design Verification Lead/ Manager with PCIe Protocol Experience: 10-12+ years of experience in IP/Subsystem level Verification. Good hands-on experience in verifying PCIe protocol (Gen4/Gen5/Gen6). Good knowledge on PCIe transaction layer, routing, reset flows etc. Good experience with AXI...
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Senior Design Verification Lead
5 months ago
Bengaluru, India Wipro Full timeHi All,We are hiring Design Verification Engineers/ Leads/Managers8 to 20+ years of experience in IP/Subsystem level Verification.Good hands-on experience in any protocol. (PCIe, DDR,USB,AMBA, Ethernet)Good knowledge on PCIe transaction layer, routing, reset flows etc.Good experience with AXI protocol, NOC subsystem verification.Good SV-UVM knowledge with...