Senior Principal Engineer STA

4 weeks ago

Bangalore Metropolitan Area, India Mulya Technologies Full time

Senior Principal Engineer/ Principal Engineer, STA (10-20 years experience)

Location: Bangalore


Join Apex Semiconductor, a disruptive startup in SoC realization, for an opportunity to revolutionize semiconductor design.

Would you like to work for an ambitious and dynamic startup company that is rapidly expanding into multiple verticals?

Are you interested in developing novel and exclusive technology in a cutting-edge industry?

Are you looking to develop and refine your expertise working with a talented and diverse team spanning across key markets?

Would you like to make your mark by contributing to new applications that will transform and improve our daily lives?

If the answer is YES, then join the Apex Semiconductor team to embark on a journey towards enabling innovative chip design solutions. We have teams in Santa Clara, California and Bangalore, India. We are looking for dynamic applicants who are driven to make a difference in the technologies of tomorrow.

You will own the block and chip level STA analysis and methodology for high performance and low power designs as well as complex SOCs.



Responsibilities

  • Block level and chip level timing analysis.
  • Timing analysis of different kinds of interfaces at chip level.
  • Work with the design and implementation teams to develop and qualify timing constraints.
  • Work on methodology development for timing analysis and timing closure.
  • Contribute to the STA flow development.
  • Work closely with the physical design engineers to resolve implementation related timing issues.
  • Create methodologies for customized timing checks for different IPs, interfaces etc.
  • Validation of library timing data (qualification of libraries).

Requirements

  • BTech/MTech from a reputed university.
  • 10-20 years of hands-on experience in timing analysis.
  • Experience in doing SoC level timing analysis.
  • Should be familiar with timing analysis for hierarchical designs.
  • Familiarity with different types of interfaces like PCIe, SATA, USB, DDR etc.
  • Worked on technology nodes 16nm and 7nm.
  • Proficiency in industry standard STA tools (Tempus and PrimeTime).
  • Good scripting skill in Tcl and Python.
  • Familiarity with different physical design tools preferably Cadence Innovus.



Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

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