Senior/ Lead Physical Design engineer

Physical Design Engineer - Senior / LeadJob Description:Strong background in digital IC design, including floorplanning, placement, routing, clock tree synthesis, and optimization.Tools Expertise: Proficient in Innovus, ICC2, and Fusion Compiler for place and route, timing closure, and physical design sign-off.Physical Design: Experience in floorplanning,...

About The JobCompany Description:MosChip Technologies is a publicly traded company with expertise in SILICON | PRODUCT | AI/ML Engineering solutions. The company has 1250+ engineers located in Silicon Valley-USA and India. MosChip offers end-to-end silicon design, verification, systems, software, and device engineering solutions, including AI/ML solution...

Are you an experienced semiconductor professional with deep, top-level (full-chip) Physical Design expertise? We are seeking a Technical Competency Lead (Physical Design) to define, evolve and champion our global PD methodologies and strategy. This is a strategic, highly influential role where your technical authority will shape how world-class ASICs are...

Senior / Lead Physical Design Engineer - EMIRJob Description:Good understanding of IR/Power-Domain-Network signoff at SOC & block level.Experience in RHSC tool.Good at scripting – python.Must have knowledge of Physical Implementation (Synthesis and Place & Route).Effective communication.Strong analytical and problem solving abilities.EMIR signoff at block...

Company Description:MosChip Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions, boasting over 1300 engineers in Silicon Valley, USA, and India. The company's expertise includes end-to-end silicon design, verification, systems, software, and device engineering, multimedia, mobility, connectivity, AI/ML solution...

Company DescriptionKriSemi Design Technologies LLC is a leading service provider to semiconductor and EDA companies, specializing in Physical Design, Physical Verification, Analog and Mixed Signal Design, and Embedded Systems. Our passionate and dedicated professionals have deep insight into VLSI challenges and focus on trending technologies with a vision...

Responsibilities:Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.Worked on 65nm or lower node...

Perform hands-on physical design and physical verification tasks across projects in advanced process nodes.Manage project-specific ASIC development flow setup and maintenance.Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate full chip...

He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have...

Position: Physical Design Engineer Experience: 4+ yrs Location: Bangalore, Hyderabad Notice Period: Preferably 0 to 45 days Summary:Strong expertise in Physical Design and RTL-to-GDSII implementation flow, including synthesis, floor planning, place-and-route, timing closure, and sign-off.Proven ability to close full-chip and block-level designs from RTL to...