DFT Engineer

DFT EngineerLocation: BangaloreNotice Period: 30 daysJob Description:We are looking for a skilled DFT Engineer with 3–5 years of experience in ASIC design and verification with a strong focus on Design-for-Test methodologies. You will be responsible for implementing and verifying DFT architectures to ensure high test coverage and manufacturability.Key...

Position: DFT Engineer Experience: 7+ years Location: Bengaluru, KA Job Description-Develop and implement DFT architecture for complex SoCs and IPs. Perform Scan Insertion, Scan Stitching, and Scan Chain Optimization. Execute ATPG pattern generation, compression, coverage analysis, and pattern debug. Implement and validate MBIST/BIST architectures,...

Position: DFT EngineerAbout the Role Experience: 5+ yearsResponsibilitiesDevelop and implement DFT architecture for complex SoCs and IPs.Perform Scan Insertion, Scan Stitching, and Scan Chain Optimization.Execute ATPG pattern generation, compression, coverage analysis, and pattern debug.Implement and validate MBIST/BIST architectures, including memory test...

We are looking for a highly experienced DFT Engineer with strong expertise in Mentor Graphics Tessent tools. The candidate should have deep hands-on experience across the full DFT flow—implementation, validation, debug—and be able to work independently on complex SoC designs.Key ResponsibilitiesPerform RTL insertion, DFT DRC checks, and debug using...

We are seeking an experienced DFT Engineer to join our ASIC/SoC design team. Thecandidate will be responsible for planning, implementing, and validating Design-for-Teststrategies to ensure optimal testability and quality of semiconductor designs. Key Responsibilities:• Design, implement, and verify DFT methodologies including Scan Insertion,MBIST, LBIST,...

Experience: 10–15 YearsWe are looking for a highly experienced DFT Engineer with strong expertise in Mentor Graphics Tessent tools. The candidate should have deep hands-on experience across the full DFT flow—implementation, validation, debug—and be able to work independently on complex SoC designs.Key ResponsibilitiesPerform RTL insertion, DFT DRC...

Purpose of the Role:The Design for Testability (DFT) engineering organization at L&T Semiconductor Technologies (LTSCT) pioneers innovative methods and technologies in the areas of DFT architecture, verification, and post-silicon bring-up of state-of-the-art semiconductor chips, such as System on a Chip (SoCs), developed using the latest semiconductor...

L&T Technology is hiring for Senior DFT Engineers / Lead DFT Engineer with 8-15 Years of experience. Job Location : Bangalore Skills Expertise should be : ATPG, SOC, ASIC DFT.

The candidate will work with 3rd party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compression. Work with physical Designers to validate the DFT timing constraints, RTL Designers to verify test design rules, Test Engineers to bring up the patterns on the ATE Automated Test...

DFT Engineer | 6-12 years| Bangalore ResponsibilitiesWill be responsible for Designing and Implementing DFT techniques.Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability.Test Modes implementation and verification, scan...