Senior STA Engineer/Lead

5 days ago

BangaloreMumbai, Maharashtra, India VIDPRO CONSULTANCY SERVICES Full time

About the job :

Location : Bangalore, Mumbai

Experience : 6+ years

Job Overview: We are looking for a skilled Senior STA Engineer or Lead with expertise in timing closure methodologies for semiconductor designs.

The ideal candidate should have a strong background in pre/post-layout constraint development, IP level constraint integration, and experience with DMSA (Design Methodology for STA) for full chip timing closure.

Custom script development for timing fixes is a must-have skill for this role.

Key Responsibilities :

- Develop and refine timing constraints for both pre-layout and post-layout stages to achieve timing closure goals.

- Integrate IP level constraints into the overall design timing closure strategy.

- Utilize DMSA methodologies and develop custom scripts to address timing issues at both IP and full-chip levels.

- Collaborate closely with RTL design, physical design, and verification teams to ensure timing requirements are met.

- Perform timing analysis, including setup and hold analysis, and work towards achieving timing closure across different modes and corners.

- Debug timing violations and drive timing closure by proposing and implementing design and/or constraint changes.

- Participate in design reviews and provide timing closure-related expertise and guidance.

Requirements :

- Bachelor's/Master's degree in Electrical/Computer Engineering or related field.

- 6+ years of experience in Static Timing Analysis (STA) with a focus on timing closure methodologies.

- Expertise in developing timing constraints for complex ASIC designs.

- Proficiency in industry-standard EDA tools such as PrimeTime, Tempus, or similar for timing analysis.

- Hands-on experience with DMSA methodologies and custom scripting for timing closure.

- Strong understanding of clock domain crossing (CDC), multicycle paths, and other timing closure challenges.

- Excellent analytical and problem-solving skills with a proactive approach to resolving timing issues.

- Effective communication skills and ability to work collaboratively in a cross-functional team environment.

- Experience with scripting languages such as Perl, Python, TCL, etc., for automation and custom script development.

Preferred Qualifications :

- Experience with low-power design techniques and their impact on timing closure.

- Familiarity with physical design concepts and methodologies.

- Knowledge of formal verification techniques and their application in timing analysis.

Benefits :

- Competitive compensation package including salary and benefits.

- Opportunity to work on cutting-edge semiconductor designs with leading-edge technologies.

- Career advancement opportunities in a dynamic and innovative work environment.

(ref:hirist.tech)

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