eNVM Bitcell Layout Design Engineer

Tata Electronics Private Limited (TEPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components.Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence.Tata Electronics is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust.’Job Summary:embedded non-volatile memory (eNVM) Bitcell Layout Design Engineer / Lead to join our growing eNVM team & spearhead the development and optimization of eNVM bitcells across wide range of Foundry CMOS technologies from 130nm to 28nm including BCD and advanced FinFET technology nodes. In this position, you are responsible for bitcell design layout and implementation of eNVM bitcells in the memory IPs to build the next generation eNVM products. This role is critical in enabling bitcell for high-yield, high-performance memory IP for a wide range of applications in automotive, IoT, and mobile markets.Qualifications:5-10 years’ experience in the semiconductor industryBachelor’s, Master’s, or PhD in microelectronics, semiconductor physics or related fieldsIdeally, 5-10 years of experience with an emphasis on memory bit cell and array layout and the characterization of memory bit cellsProficient in the use of common EDA tools like Cadence or Calibre for layout design including verification by DRC and LVS etc.Basic knowledge of the functionality of memory bit cells and arrays like SRAM, MRAM, RRAMKnowledge & good understanding of components included in PDKExperience with bench measurement is preferredGood understanding of planar & FinFET CMOS flows is preferredResponsibilities:Design of eNVM bitcell layout (eFuse, eFlash, RRAM, MRAM) across wide range of foundry processes (130nm to 28nm & FinFET)Creation, optimization, verification of bitcell kits for each eNVMRoot cause analysis of problems with devices and bitcells along with documentation of these test structures Driving improvement of infrastructure for bitcell kit and SLM creation and verification Evaluation of foundry PDK changes & providing expert advice to the design team on their impact on eNVM designAnalysis of incoming mask sets with respect to memory bitcell contentWork with design & layout teams to fix (or justify waiving) the violations. Keeping track of changes across design manualWork with different engineering teams with diverse disciplines across multiple geographic areas and time-zonesBasic understanding of ESD & latch-up prevention techniques to advice design & layout teamsProlific in developing indigenous IP and filing disclosuresDesired Attributes:For lead position, it is expected to have strong leadership skills with experience in mentoring and motivating high-performing teamsEffective communicator and collaborator across global, cross-functional groupsInclusive and adaptable to diverse cultural and professional environmentsCurious, resilient, and data-driven in approaching challengesBuilds strong relationships and offers support with humilityInnovative and agile, quick to explore new ideas and embrace change