Senior Layout Engineer

2 hours ago

india, IN Best NanoTech Full time

Senior Analog Layout Engineer (8–17 Years Experience)

Location: Hyderabad / Remote

Job Type: Full-Time


About the Role:

We are looking for a highly experienced Senior Analog Layout / IP Delivery Engineer with strong expertise in designing and integrating high-speed analog IPs at the chip level. This role requires deep knowledge of ICC2-based top-level integration, extensive IP verification experience, and the ability to run block-level simulations independently. The ideal candidate will take full ownership of IP development, verification, integration, and delivery—including foundry coordination, signoff, and tape-out.


Key Responsibilities:

Analog Layout & Integration

Lead chip-level planning and integration of high-speed analog IPs.

Execute complete analog layout design including floor planning, routing, device matching, shielding, EM/IR checks, and parasitic optimization.

Run post-layout simulations (corners, Monte Carlo, extracted netlist) and ensure correlation with schematic.

IP Verification & Signoff

Own the entire IP verification process: DRC, LVS, ERC, ANT, PEX, and reliability checks.

Ensure zero-violation GDS delivery for IP signoff.

Work closely with foundry teams on PDK clarifications, rule updates, model issues, PEX discussions, and tape-out requirements.

Cross-Functional Collaboration

Coordinate with PD, DV, circuit design, packaging, and integration teams for seamless IP delivery.

Prepare and deliver comprehensive IP documentation, abstracts, verification reports, and final GDS.

Process & Technology Expertise

Mandatory hands-on experience with TSMC 5nm.

Strong understanding of ICC2 flows for complete SoC/top-level integration.

Ability to run extracted and post-layout simulations for designed blocks.


Required Skills:

8+ years of proven experience in Analog/Mixed-Signal Layout.

Deep expertise in high-speed IPs: SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks.

Strong understanding of chip-level hierarchy, integration, and physical interfaces.

Proficiency in Cadence Virtuoso, PVS, Calibre, and extraction tools.


In-depth knowledge of:

DRC/LVS/ERC

PEX & RC Extraction

Signoff decks and reliability checks

Experience interfacing with foundry teams for rule clarifications and tape-out signoff.

Strong sense of ownership in IP development, customer communications, and documentation.


Good to Have:

Experience with other advanced process nodes (7nm/3nm).

Exposure to SERDES/PCIe/MIPI/USB high-speed IPs.

Experience working with global clients.

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