Senior Physical Design Lead

Hi All,Eximietas Hiring Senior Physical Design Leads/Managers.Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.About the jobQualification Required:Typically requires a minimum of 10+ years of experience in Physical Design with mainstream P&R toolsBachelors OR Masters...

Hi All,Eximietas Hiring Senior Physical Design Architects.Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.About the jobQualification Required:Typically requires a minimum of 10+ years of experience in Physical Design with mainstream P&R toolsBachelors OR Masters Degree...

Hi All,Eximietas Hiring Senior Physical Design ArchitectsExperience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.About the jobQualification Required:Typically requires a minimum of 10+ years of experience in Physical Design with mainstream P&R toolsBachelors OR Masters Degree...

Hi All,Eximietas Hiring Senior Physical Design Leads/Managers (EMIR).Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.About the jobQualification Required: (EMIR).Block / Subsystem / Partition• Role: EM/IR.• EDA Tool: Redhawk & Node: TSMC 3nm / 5nm.• ESD resistance,...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the...

Hi All,Eximietas Hiring Senior Synthesis/Constraints.Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Block / Subsystem / Partition / Full chip.• Role: Synthesis and Timing Constraint Engineer.• EDA Tool: Cadence Genus & Fishtail.• Node: TSMC 3nm / 5nm.• UPF...

Job Description:We are seeking a Physical Design Lead with strong expertise in RTL-to-GDSII flow for advanced technology nodes (7nm and below). The role involves leading SoC/IP physical implementation, driving PPA goals, and ensuring successful tapeouts. You will manage a team, interface with cross-functional groups, and own block/top-level execution.Key...

Job SummaryWe are seeking a highly experienced Senior Physical Design Engineer with a minimum of 10 years in the RTL to GDSII flow. This role requires hands-on expertise with Cadence Innovus, experience at N3 and below process nodes, and strong scripting and flow debugging skills. Key ResponsibilitiesLead physical design activities from RTL to GDSII,...

Hello Folks, we at LTTS are looking for Physical design Lead role with 8+ years of experience. Deatiled JD is below as mentionedCandidates with PnR – 8+ ’ experience • IP/Block level PnR activities from Netlist to GDS-II. • Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV,...

Role Overview:Job Title : PNR LeadExperience : 8+ YearsWork location : BangaloreJob Description:Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks...