Microarchitect And Rtl Design Engineer

Hands-on experience in SoC-level FPGA prototyping, design, and verification.Execute FPGA Bring up on industry-standard FPGA Prototyping systems like Synopsys HAPSStrong knowledge of emulation platforms like Cadence Palladium, Synopsys ZeBu, or Mentor Veloce.Expertise in ASIC-to-FPGA / Emulation— clocking, resets, and memory model integration IO Modeling...

SummaryWork on physical implementation of state-of-the-art SOCs at cutting edge FinFET technology nodes for various customers.This position is for a senior-level physical design engineer who will work onPhysical implementation of a complex SOC – Synthesis, Floorplan, P&R, Sign-offWork hands-on to solve critical design and execution issues related to...

We’re Hiring – Lead Design Verification Engineer @ Eximietas Design! Position: Lead Design Verification EngineerExperience: 7+ YearsLocations: Bangalore / Ahmedabad / Pune / HyderabadKey Skills:Proven experience in Design Verification using SystemVerilog and UVMStrong experience in minimum 2 protocols like AXI, AHB, Ethernet, PCIe, UCIe, DDR, USB, NVMe,...

Hi Folks,Greetings from Mirafra Technologies! We are looking for Senior DFT Engineers with strong expertise in ASIC/SOC DFT implementation. Experience: 7+ Years Notice Period: 0–30 Days (Immediate Joiners Preferred) Location: Noida / BangaloreKey Skills:DFT Architecture, Scan Insertion, ATPG, MBIST, LBISTExperience with Synopsys / Tessent / Mentor DFT...

Location- Bangalore/ Noida/ Hyderabad4+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Synthesis Quality with FE Inputs, LEC environment, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff.USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing...

Job Title: Senior Hardware Verification Engineer Location: Bangalore, IndiaAbout the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our...

Physical Design Engineer (Cadence Innovus) – Bangalore Experience: 3+ Years | Notice Period: Immediate to 30 DaysJob Description: Hiring Physical Design Engineers with hands-on experience in Cadence Innovus and low-power design implementation for end-to-end ASIC flow.Key Skills:Floorplanning, Placement, CTS, Routing, Timing ClosureDRC/LVS, Power & IR Drop...

Senior/Principal Memory Design EngineerLocation: Bangalore, IndiaExperience: 10+ YearsAbout ACL DigitalACL Digital, part of the ALTEN Group, is a next-generation product engineering and semiconductor services company with global presence across 30+ countries. We specialize in ASIC/SoC design, memory IP, verification, embedded systems, automotive, 5G, AI/ML,...

ACL Digital is hiring for PD and STA Engineers for Bangalore and Location.3+years of experience in Physical Design.Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.Notice period- Immediate to 30 days

Role: Lead Verification EngineerExperience : 8+ yearsLocation : BangaloreResponsibilities:Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.Integrate and verify IPs like AXI4,...