DV Engineer(GLS)

Role:Design Verification EngineerSkill: DV with GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV-IP with Ethernet/PCIENP: Immediate to 30 daysLoc: HYDExp: 10+ yrsRole:Design Verification EngineerSkill: DV with Soc, GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV with...

Role:Design Verification EngineerSkill: DV with GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV with Soc, Arm ProcessorNP: Immediate to 30 daysLoc: BLRExp: 6+ yrs

Responsibilities: Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to...

Job Requirements Job DescriptionResponsibilities:Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:Active involvement with architecture team during the spec definition phaseVerification strategy definition along with Verification plan...

Desired Profile :B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.Expertise in execution and debugging of test-suites at the GPU sub-system levelExpertise in GLS (Gate-Level Simulation)Expertise in writing assertions and test benches using system verilogExpertise in UVM methodologiesExpertise in Test planningExpertise in sub-system...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design...

We require 1.DV-Formal verification with must Jasper Gold Exp Exp : 5+Location : BLR/Pune2. DV- WIFI/ Wireless / BT with Test case Dev/debuggingExp : 5+Location : BLR/Pune3. DV- PCIE with Test case Dev/debuggingExp : 5+Location : BLR/Pune

We are hiring DV Contract Engineers with 10+ years of experience in UVM-based testbenches, netlist/gate-level simulations, and datapath blocks. Strong expertise in Cadence tools (Xcelium/Simvision) and scripting (Python/Shell) required. Required Candidate profileExperienced DV engineer with 10+ years in verification, UVM testbench, Cadence tools...

General Summary:QCT's Bangalore Wireless R&D(WRD) HW team in Bangalore is looking for experienced Wireless HW design verification engineers to work on Qualcomms best in class chipsets for mobile phones, wearables and IOT . Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work...

Role : DV Senior EngineerExperience : 5–9 years of experienceWork location: BangaloreWork mode: Work from officeInterview process: 1 HR round , 2 Technical roundShould be open for virtual and face to face interview as required by the clientResponsibilities:Implement and debug DV environments and stimuli.Analyze coverage and contribute to test plan...