Design Verification Engineer/Lead
2 weeks ago
4-10 years
Role and responsibility:
Strong Verification experience at Subsystem or SOC levelStrong in System Verilog, Verilog, UVM, C/C++, ScriptingStrong debugging skills, problem solving skills.
Good attitude , good team player with strong interpersonal skillsPower Management, Graphics Domain experience preferredCandidate must have low power verification experience inintel(ODC)/AMD(ODC) projects.
Academic QualificationBTech / Mtech Electrical/Electronics/Computers
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