Staff Engineer

1 week ago

Noida, Uttar Pradesh, India Renesas Electronics Full time
Job Description

Projects cover various business areas, and designs must meet different power/performance/area objectives, depending on the product. Cooperation and teamwork across global locations are crucial as aligning approaches is vital and sharing resources is common. Strong technical, communication, and consensus-building skills, along with the ability to influence decisions across a worldwide organization, are necessary.

  • Contribute to the Verification R&D team focused on technical execution and state-of-the-art methodologies for advanced microcontrollers and microprocessors design.
  • Collaborate closely with system architects to define high-level implementable and robust specifications.
  • Engage with verification/validation teams to ensure design quality and robustness.
  • Foster strong collaboration with other R&D teams like Verification, digital IP, Design Enablement, Emulation, and Validation to reach project milestones.
  • Promote continuous enhancement of design methods to guarantee flawless chips.
  • Engage with SMEs and key leaders in various technical areas to influence design enhancements and verification methods.
  • Contribute to top-notch verification methodologies by collaborating with global internal and external experts and driving adoption and compliance processes. Focus on innovative strategies to boost efficiency and quality, impacting R&D and ROI significantly.
  • Participate in customer engagements to evaluate quality and risks.
Qualifications
  • Degree in Electrical Engineering or Computer Science, with over 5 years of IP/Sub-System Verification experience.
  • Skills in testbench design and UVM methodology application for IP/Subsystem and SOC.
  • Familiarity with Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency.
  • Proficiency in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.
  • Solid knowledge of Verilog, System Verilog, C/C++, Shell.
  • Experience with scripting languages such as Perl, TCL, or Python is a plus.
  • Proficient in Metric Driven Verification concepts, functional and code coverage.
  • Expertise in directed and constrained random methodologies.
  • Good understanding of formal verification methods and assertions.
  • Experience in debugging pre- and post-silicon designs in simulation and on the bench.
  • Strong written and verbal communication skills.
  • Familiarity with System Verilog and front-end tools (simulation, waveform viewers, lint, CDC, RDC, etc.) is necessary, along with highly efficient FE methodologies.
  • Experience with complex multi-core SoCs with extensive interconnects and various peripherals is preferred.
  • Knowledge in clocking, system modes, power management, debug, security, and other architectures is a plus.
  • Experience with High-Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems would be beneficial.
Additional Information

Renesas Electronics Corporation aims for a safer, smarter, and more sustainable future where technology simplifies our lives. As a leading global microcontroller provider, Renesas leverages expertise in embedded processing, analog, power, and connectivity to offer complete semiconductor solutions. These Winning Combinations speed up the arrival of automotive, industrial, infrastructure, and IoT applications, connecting billions of intelligent devices that enhance how people work and live. Discover more at

Renesas' mission, To Make Our Lives Easier, is supported by the company culture, TAGIE, representing Transparent, Agile, Global, Innovative, and Entrepreneurial values. The aim is to integrate this unique culture into all operations to thrive as a company and establish trust with colleagues, customers, and stakeholders.

Renesas Electronics is dedicated to diversity and maintaining a discrimination-free work environment respecting various backgrounds. Read more about our Diversity & Inclusion Statement for further details.

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