Sr. Engineer Design For Testability

2 weeks ago

Bengaluru, Karnataka, India L&T Semiconductor Technologies Full time
Role - DFT Engineer /Sr. Engineer
Stream - R&D

Company Overview:


L&T Semiconductor (LTSCT), a fully owned subsidiary of L&T is the first Indian Semiconductor product company - a fabless company designing & delivering Smart Devices for Global Customers.

A company that provides Semiconductor Devices and Technology partnership by helping customers realize energy efficient, high-performance systems to benefit from data, electrification and software defined technology trends.

Our aim is to build an India-based semiconductor portfolio of Smart Devices across MEMS Sensors, Power, Analog Mixed Signal & RF products, to support Automotive, Industrial, Energy and Telecommunication verticals.

We have a presence four prominent geographies US, Europe, Japan and India, with offices in Austin, Munich, London, Tokyo, Bangalore and Chennai.


Our Mission:
Enabling our customers with a new generation of smart, efficient and market leading power, sense and control Integrated Circuits. Together, creating smart applications and driving decarbonization and digitalization.

Purpose:
We are seeking a talented VLSI DFT Engineer with 4-8 years of experience to join our team.

As a VLSI DFT Engineer, you will play a key role in Design for Test (DFT) SoC ATPG for our advanced VLSI SoC designs.

The ideal candidate will have a strong background in scan insertion, ATPG.

Areas Of Responsibility:


Design for Test (DFT) engineering organization at L&T Semiconductor Technologies (LTSCT) works on ground breaking methods & technologies for innovations in DFT architecture, verification & post silicon bring up of state-of-the-art semiconductor chips like system on a chip (SOCs) built on the latest semiconductor technology nodes.


Responsibilities:
Implement scan insertion, ATPG pattern generation.
Conduct DFT simulations and analyse results to ensure test coverage and quality.
Debug and resolve DFT-ATPG related issues throughout the design process. Analog BIST implementation for selected Analog blocks like PLLs, ADC & DACs.
IOBist methods implementation for IO structures of the SOCs.

You will work with cross-functional teams like design, physical design, verification teams to deliver the DFT solutions to the SOCs in predefined schedule.


Experience and Qualification:
4-8 years of experience in VLSI DFT, preferably in a semiconductor or integrated circuit design environment.
Proficiency in industry-standard DFT tools such as Mentor Tessent , Synopsys DFT Compiler, Cadence Encounter Test.
Strong understanding of scan insertion techniques, ATPG algorithms .
Experience with DFT simulation tools and methodologies, including fault modeling and coverage analysis .
Familiarity with industry standards such as IEEE JTAG) and IEEE 1687 (IJTAG).
Effective communication and teamwork skills, with the ability to collaborate across functional teams.
Qualifiers for the Role / Necessary Experience and Skills Required for the Role:
Bachelor or Master's degree in Electronics engineering, Electrical Engineering, Computer Engineering, or related field.
Experience with advanced DFT techniques such as hierarchical DFT and low-power DFT.
Familiarity with scripting languages such as TCL, Perl, or Python for DFT automation.
Knowledge of post-silicon DFT activities such as test pattern compression and silicon bring-up.

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