Staff Asic Design Engr
2 weeks ago
We are looking for experienced FPGA Verification Engineer.
Roles & Responsibilities:
- Must have 38 years of experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, subchip and chip levels.
- Must have strong HVL coding skills for Verification and be handson with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools.
- Exposure to UVM (or similar) verification methodologies is required.
- Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired.
- Working knowledge on HW (board or equivalent platform) is preferred. Working knowledge of RTL design is preferred.
- Should be conversant with technologies like, Ethernet, PCIe etc. Knowledge of telecom protocol is preferred.
- Structured and thorough with analytical and troubleshooting skills.
- Good written and oral communication skills are required.
- Flexible, innovative, selfdriven and willing to take own initiatives.
- Highly motivated team player.
We offer:
- A high pace in development of new products.
- Tight cooperation with other disciplines.
- Short product development cycles, Real results of your work, you will see how it affects our products and sales.
- International possibilities of development and internal advancement.
- Social and wellness activities and clubs.
- A friendly and helpful atmosphere.
- Highly competent and motivated colleagues.
- Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to_
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