Senior Engineer
7 days ago
Position Title : Senior Engineer - ASIC Design Verification
Location :
Period : Immediate to 15 days
Role & Responsibilities :
- An expert level with developing UVMbased SV testbenches.
- Highly experienced with defining block, subsystem and SOC top level test plans.
- Relevant experience with one or more of PCIe, NVMe, NAND, DDR and CPU subsystems.
- Deep understanding and knowledge of verification methodologies, flows and quality metrics
- The incumbent will be responsible for executing complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, indepth technical reviews, and close tracking of technical as well as management SKILLS &
EXPERIENCE :
At-least 4 years of experience in System Verilog HVL.
- Atleast 4 year of experience in OVM/UVM/VMM/Test Harness.
- Hands on experience of developing assertion, checkers, coverage and scenario creation.
- Must have executed atleast 1 SoC Verification project
- Experience in developing test and coverage plan, Verification environment and validation plan.
- Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is
BACKGROUND :
B.E./ B.S./ B.Tech/ M.S./ M.Tech in Engineering.
)
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