VLSI - Synthesis and Static Timing Analysis - Senior Design Engineer

7 days ago

Delhi, Delhi, India Eteros Technologies Full time

Company:
Eteros Technologies India Private Limited
Eteros Technologies, Inc. is a pioneering Semiconductor Engineering services company, with its headquarters located in Silicon Valley's heart, San Jose, CA, USA. Eteros Technologies India Pvt Ltd operates as a wholly owned subsidiary with offices in Bangalore, Noida, Hyderabad, and Ahmedabad.

  • The clientele of Eteros includes some of the most esteemed names in the semiconductor industry, ranging from top 20 semiconductor startups to well-reputed publicly traded companies.
  • Eteros engineers are engaged in cutting-edge technology nodes within the AI/ML, Datacenter, Automotive, and 5G sectors. Working alongside bright and accomplished engineers and leaders worldwide presents a unique opportunity for young Eteros engineers to demonstrate their skills globally from the outset while learning from industry-leading companies.
  • Unlike traditional design services firms that offer staff augmentation, Eteros treats its engineers as essential team members who actively contribute to turnkey projects in Implementation, Digital and Mixed Signal Verification, DFT, and Analog Design and Layout. Collaborating closely with customers, Eteros and its engineers influence methodologies and design processes.
  • Eteros emphasizes the continuous growth and development of its engineers, both on and off the job. The company is dedicated to preparing its employees for accelerated career progression and long-term success.

Job Title/Role:
Synthesis and Static Timing Analysis - Senior Design Engineer

Location :
Bangalore/Hyderabad/Ahmedabad

Experience

Level : 3+ Years

Industry :
Semiconductors

Employment

Type :
Full-time

Job

Functions :
Engineering

Summary

As a key member of a development team, you will spearhead the synthesis, static timing, and DFT efforts for a cutting-edge mixed-signal chip designed for a prominent Silicon Valley startup.

In this impactful role, you will collaborate closely with various teams to ensure timely delivery of functional products to customers, making a significant contribution to SOC design efforts in a rapidly evolving industry.

By joining as a Sr, ASIC STA Engineer, you become part of the SOC digital design team responsible for delivering integrated solutions in a growing market.

Key Qualifications
Deep understanding of ASIC design timing closure flow and methodology is essential for this position.

  • BTech/MTech/PhD with a minimum of 4+ years of hands-on experience in generating ASIC timing constraints and achieving timing closure.
  • Proficiency in STA tools (Tempus and Primetime) and timing closure methodologies, with a solid grasp of OCV, noise, and crosstalk effects on timing.
  • Familiarity with all aspects of timing closure for high-performance mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm.
  • Understanding of timing corners/modes and process variations.
  • Knowledge of low-power techniques such as clock gating, power gating, and millivoltage designs. Skilled in scripting languages (Tcl and Perl).
  • Experience with ECO timing flow
  • Excellent communication skills are crucial as the role involves extensive interaction with diverse groups (e.g., digital design, verification, DFT, physical design, etc.).
  • Knowledge of RTL, synthesis, logic equivalence, DFT, floor-planning, and backend methodologies and tools.
  • Ability to solve intricate problems and autonomously drive tasks to completion efficiently.
  • Capability to work independently with minimal supervision and take full accountability.
Responsibilities Include

  • Taking ownership of full chip and block-level timing closure throughout the project cycle (RTL, synthesis, and physical implementation).
  • Developing and enhancing methodology and flows related to timing verification and closure.
  • Generating block and full chip timing constraints.
  • Analyzing timing reports and using scripting techniques to gain insights and facilitate timely timing closure.
  • Supporting digital chip integration tasks and workflows.
What's in it for you

  • Engage with cutting-edge technologies
  • Opportunities for career advancement and personal growth
  • Competitive remuneration package
  • Comprehensive medical benefits and more

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