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ASIC Verification Engineer

3 months ago

Pune, Maharashtra, India Cientra techsolutions Full time

Required ASIC/RTL design verification engineerExperience:

  • 3-10 yrsNotice period:
  • immediate to 90 daysSalary:
  • as per companySkills
  • Strong knowledge of SV and UVM


The purpose of the role is to develop modules in the company's next generation of ASICs for Radioequipment and Radio Access Network compute.

These modules perform advanced signal processing.
This role includes test bench systemization, UVM test case development, verification, and productdocumentation.

Required skills:

  • UVM Verification
  • ASIC Verification
  • System Verilog
  • Scripting
  • Verification
  • Product documentation