SoC Design Manager
3 weeks ago
Physical Design Managerwww.Omnidesigntech.ComLocation: Bengaluru /HyderabadAbout Omni Design TechnologiesOmni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts.Omni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers.Physical Design ManagerHyderabad / BangaloreSOC Development – Engineering /Full-time /HybridOmni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers.Omni Design is developing exciting high-speed Mixed-Signal SOC. We are looking for a Lead/Manager of Physical Design to make these high performance Mixed-Signal SOCs a realityRole and ResponsibilityOwn and drive the physical implementation of next-generation Mixed-Signal SOC with HS ADC/DAC, HS interfaces like PCIe, LPDDR, MIPI, USB2/3, Gig Ethernet etc.Understand the requirements and define physical implementation methodologies.Collaborate with architecture, design, front end and CAD teams to deliver high-quality physical designs.Implement and verify designs at all levels of hierarchy in the SOC.Interact with foundry over matters of technology, schedule, and signoff Qualifications and ExperienceBSEE Required, MSEE Preferred8+ years of experience of physical design in SOCs.3+ years of experience in managing projects and leading teams.Hands-on expertise in all of the following areas: Floorplanning, Power planning, Implementation of UPF Methodology, Logic and clock tree synthesis, Placement, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IRFull chip/ top-level expertise in multiple chip tape-outs.Good understanding and experience in SCAN, BIST, and ATPG.Strong background in TCL/Perl/Python programming is a must.Expertise in double patterning process nodes is desirable. Experience with sub 40 nM nodes requiredExpertise in Cadence or Synopsys RTL-to-GDSII flow is preferred.ExpectationsDo the FC Floor Plan and LayoutSet up the EDA tools and develop the scriptsDevelop the UPF methodologyImplement the Power, Clock GridGenerate the SDF filesDo the DRC, ERC, LVS, SI and Cross talk checks, Do the DFM checksTapeout the chipManage and mentor the PD and custom layout teamMake changes, as needed to the custom layout of the IPRelease the GDS2 to the FabsContact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"
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