DFT

📌 Job Title: DFT Engineer / Senior DFT Engineer / Lead / Manager / Staff EngineerExperience Range: 3 – 17 Years Location: Bangalore / Chennai Notice Period: Immediate to 90 Days Open Positions:Lead / Manager – 4 PositionsJunior & Mid-Level – 20 Positions (For multiple Customer-Based, In-House & Turnkey Projects)📧 Send Profiles to: prabhu.p@acldigital.comAbout the RoleWe are hiring passionate Design-for-Test (DFT) professionals to work on next-generation semiconductor SoCs, cutting-edge nodes, and high-volume production silicon. The role involves ownership of DFT architecture, implementation, signoff, silicon bring-up, and test quality optimization. Opportunities available across Automotive, AI/ML, Networking, 5G, Storage, Consumer & High-performance Computing domains.Key ResponsibilitiesDepending on experience level (Junior/Mid/Lead/Manager/Staff):Ownership of DFT architecture, planning, integration & verificationDevelopment of Scan/ATPG/MBIST/JTAG/BSCAN/Boundary Scan logic and flowsDFT insertion, pattern generation, fault coverage analysis and sign-offWork with RTL, Physical Design, STA, and Silicon Validation teamsATPG coverage improvements, debugging and yield enhancementMemory BIST architecture and test algorithm integrationPost-silicon bring-up, ATE vector debug, production ramp supportDrive DFT methodologies, automation & best practices across projectsMentoring juniors, project planning & customer interaction (Lead/Manager roles)Mandatory Technical SkillsCandidates should have experience in one or more DFT areas:✔ Scan Insertion, Compression & ATPG ✔ JTAG/BSCAN/Boundary Scan/IEEE 1149.x ✔ MBIST/Logic BIST/Analog & Mixed-Signal BIST ✔ ATPG pattern debugging, DRC/Lint fixing, STA timing for test modes ✔ DFT Sign-off & Coverage closureTool Experience (preferred): Siemens Tessent, Synopsys TetraMAX, D-Compiler, Modus, Genus, SMS, FastScan, TestMAX, Shell scripting, Python/TCL for automationNice to Have / Emerging & Future DFT Technologies(To attract advanced profiles & future-ready talent)🔹 DFT for 2.5D/3D-IC & Chiplets (UCIe/OpenHBI testing frameworks) 🔹 AI-Driven ATPG optimization & test time reduction 🔹 DFT for RISC-V Architectures, Automotive ASIL standards 🔹 Logic-Diagnosis, Scan-Compression Innovations 🔹 LBIST for functional safety / ISO26262 compliance 🔹 Design-for-Security (DFSec) – Secure JTAG, PUF, Anti-tamper DFT 🔹 Silicon lifecycle management, Telemetry-based test analytics 🔹 Yield ramp modeling & ML-based failure predictionWho Should Apply?We are looking for engineers who:Have strong fundamentals in digital/ASIC/SoC design & testAre passionate about innovation in DFT, automation & scalable methodologiesEnjoy solving complex silicon challenges across latest technology nodesCan work in a fast-paced environment with global customersPerks & Career GrowthWork on advanced nodes (7nm → 3nm → 2nm) and cutting-edge SoCsOpportunity to contribute to future-ready DFT workflows & R&D initiativesLeadership & customer-facing roles for high performersExposure to In-House, Turnkey & Global Tier-1 Semiconductor projects📨 If you are eager to shape the next era of silicon, drop your resume at: 📧 prabhu.p@acldigital.com