Digital Engineering Lead

Digital Design Managerwww.Omnidesigntech.ComLocation: Bengaluru / HyderabadAbout Omni Design TechnologiesOmni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts.Digital Design ManagerHyderabadSOC Development – Engineering /Full-time /HybridOmni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers.The Manager of digital and mixed-signal engineering will be responsible for development of mixed-signal SOC being developed at ODT and build the digital engineering team and will work Analog/RF engineering, FW engineering, verification, Systems Validation team, Operations, SOC Architects, and report to the Director of ASIC Engineering.Roles and ResponsibilitiesManage digital team, hire, and retain best talentLead SOC integration design team to develop and productize next generation mixed-signal RF/communication SOCsWork with cross-functional project teams to define product specifications, system architecture, HW/SW partitioning, and execution planImplement best SoC development practices and improve design methodology to maximize efficiency and predictabilityDeliver chip architecture, design, integration, programming model, verification, and manage hand-off to backendSupport Silicon and System Validation, support system integration, and production testingDrive innovation and provides leadership to the organization to ensure world-class system solutions and flawless executionQualificationsBSEE Required, MSEE PreferredProven track record of success in high-performance/high-volume semiconductor industrySoC, embedded CPU and bus architectures, networking, and control interfacesCommunications / DSP algorithms and power / area efficient implementationsDigital IC design, design for low power and high speed, design for test (DFT)System modeling, RTL coding, Lint / CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence / Synopsys design environmentsDirected and constrained random verification, UVM methodologyEmbedded systems FPGA emulation, lab debug and chip validationProject planning and execution, and performing design tradeoffs to achieve performance, power, die size, and schedule targetsSelf-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast-paced environmentSenior Management experience preferredWork with architecture, physical design, and design teams to lead the implementation of the digital architecture.Develop and refine specification of the micro-architecture for the digital architecture.Is in tune with industry trends and contributes to consistent roadmap decisions.Experience10+ years of experience in the area of RTL design and verification of siliconAt Least 3+ years experience in leading low-power mixed-Signal SOC design10+ years of experience with FPGA architecture specification and design (Altera or Xilinx) for high-speed serial protocols, including USB-SS, PCIe, SATA/SAS, DisplayPortExperience in leading, specifying, and work with Analog/RF team in developing, verifying, and productizing SERDES, CDR, and PLL/DLL designsExperience with USB 3.0, DisplayPort, PCIe, or SATA based silicon designs preferredStrong background in analog/mixed-signal integrated SOC DevelopmentStrong Hardware design knowledge and familiarity with signal integrityStrong foundation in SoC architecture, design, verification and physical implementationStrong analytical problem solving, and attention to detailsKnowledge of wireless, mobile, and storage domainsExpertise in Verilog/System Verilog, C/C++/SystemC, UVM, Scripting languages like Perl/Python, etc.Excellent technical documentation skillsExcellent written and verbal communication skillsExcellent interpersonal skills, self-motivated, self-starterExperience in startup environmentExpectationsPut the RTL for the Full chip together.Evaluate the IP we have to license – like PCIe, LPDDR4, JESD 204C PHYHelp develop any BISTWork with Verification Team to develop the FC Simulation test suitesDevelop the RTL for the various state machines and interfacesRun a few of the simulationsHelp with the FC simulations debugHelp close the timing issues if any come up and work with the PD person to resolve any SI issues.Be a mentor and lead a team of Digital design engineersWork with Systems and Test engineering team to help validate the parts and release them to productionContact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"