Silicon validation Engineer Exp: 3- 8 yrs

1 day ago


Mount Abu, Rajasthan, India LeadSoc Technologies Pvt Ltd Full time

Greeting from LeadSOC Technologies_ Hydarabad

Role: Post Silicon Validation Engineer

Experience: 3 – 8 years

Location: Hyderabad, On-site

Notice Period: Immediate Joiners

Responsibilities:

  • FPGA Design Flow & Validation
  • RTL Design, Implementation, and Protocols (PCIe, Ethernet, DDR4/5, Memory)
  • Integration-focused role: 80% Integration, 20% Design
  • System-level Testing & Design
  • Silicon Validation
  • Debugging Interfaces and Design-level Debugging
  • Board-level Debugging (20:80 simple design & debug split)

Requirements:

  • Strong knowledge in RTL design and implementation
  • Expertise in FPGA design flow and validation
  • Experience with system-level testing and silicon validation
  • Hands-on exposure to debugging (board level & design level)
  • Familiarity with Xilinx / Intel toolchains
  • Understanding of protocols: PCIe, Ethernet, DDR4/5, Memory

Regards'

Murali



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