Logic MicroArchitect:

4 weeks ago

Greater Bengaluru Area, India Mulya Technologies Full time

SoC MicroArchitect:

Location: Bangalore

We are looking for someone who will lead the development of high-speed cutting-edge SerDes design. As the lead of the micro-architectural definition and design implementation, the selected candidate will drive logic chip design achieving data of 16Gbs and above.


SoC Micro-Architect, you will play a key role in the design and development of complex ASICs and System-on-Chip architectures for various electronic devices. You will be responsible for defining the microarchitecture of the SoC, optimizing performance, power efficiency, and area constraints while ensuring compatibility with system-level requirements. You will also need to define and validate analog-digital interfaces.


As an SoC Micro-Architect, you will play a key role in the design and development of complex ASICs and System-on-Chip architectures for various electronic devices. You will be responsible for defining the microarchitecture of the SoC, optimizing performance, power efficiency, and area constraints while ensuring compatibility with system-level requirements. You will also need to define and validate analog-digital interfaces.


Experience: 12+ years

Responsibilities:

  • Microarchitecture Design: Define the high-level microarchitecture of the SoC, including processor cores, memory subsystems, interconnects, and other on-chip components.
  • Performance Optimization: Work closely with design teams to optimize the performance of the SoC through architectural enhancements, pipeline optimizations, and system-level optimizations.
  • Power Efficiency: Implement power-efficient design techniques at the microarchitectural level to meet strict power budgets and extend battery life in mobile and embedded applications.
  • Area Optimization: Optimize the area utilization of the SoC by designing efficient microarchitectural components and minimizing silicon footprint without compromising performance or functionality.
  • Interface Design: Define interfaces between various on-chip components, including processor cores, memory controllers, peripheral interfaces, and accelerators, ensuring efficient data transfer and low latency.
  • Technology Evaluation: Evaluate emerging technologies, design methodologies, and architectural innovations to improve the performance, power, and area efficiency of future SoC designs.
  • Performance Analysis: Perform performance analysis and simulation of the SoC architecture using industry-standard tools and methodologies, identify performance bottlenecks, and propose optimizations.
  • Collaboration: Collaborate with cross-functional teams including hardware architects, RTL designers, verification engineers, software developers, and system integrators throughout the design process.
  • Documentation: Document the microarchitecture specifications, design decisions, performance trade-offs, and implementation details for internal and external stakeholders.
  • Technical Leadership: Provide technical leadership and guidance to junior architects, design engineers, and cross-functional teams to ensure successful delivery of SoC projects.


Qualifications:

  • Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
  • Serdes experience and mixed-signal IP experience is a must.
  • Solid understanding of computer architecture principles, including CPU, GPU, memory hierarchy, and interconnect architectures.
  • Proficiency in hardware description languages (Verilog, VHDL) and microarchitecture modeling tools (SystemVerilog, SystemC).
  • Experience with SoC design methodologies, including RTL design, synthesis, timing analysis, and physical design.
  • Strong analytical and problem-solving skills, with the ability to analyze complex system-level trade-offs and make data-driven decisions.
  • Excellent communication and teamwork skills, with the ability to collaborate effectively with cross-functional teams in a dynamic environment.
  • Prior experience in SoC microarchitecture design, processor design, or related fields is a plus.


Experience:

12+ Years of experience in PCIE G3/G4/G5 or MIPI CSI/DPHY and Display Port.

Must be familiar with the PHY Logic design challenges

Must understand the protocol

Must be a hands on person

Join a team which is in the automotive space and a fun work environment.


Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"

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