Design Verification Engineer

4 weeks ago

Kochi, India HCLTech Full time

Key Responsibilities:

  • Develop and execute verification test plans based on design specifications.
  • Create constrained-random and directed testbenches using SystemVerilog/UVM.
  • Develop functional coverage models and drive coverage closure.
  • Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues.
  • Perform block-level and/or SoC-level verification.
  • Integrate and verify 3rd-party IPs and custom IPs in subsystem and full-chip environments.
  • Collaborate with RTL, DFT, DV, firmware, and physical design teams.
  • Run regression simulations and ensure verification quality through coverage metrics.
  • Automate verification flows and improve efficiency using scripting languages.

Required Skills & Experience:

  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related discipline.
  • 4–10 years of experience in digital design verification.
  • Strong knowledge of SystemVerilog and UVM methodology.
  • Good understanding of digital design concepts, RTL, and timing.
  • Experience in using simulators like VCS, Incisive/Xcelium, Questa, etc.
  • Hands-on experience with code and functional coverage, assertions, and checkers.
  • Exposure to industry-standard protocols (AXI, AHB, I2C, SPI, PCIe, DDR, etc.).
  • Experience in debugging RTL issues using waveform viewers (e.g., DVE, SimVision).
  • Strong scripting skills in Python, Perl, Shell, or Make.

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