Principal STA Engineer
1 month ago
Principal STA Engineer
Client: Top10 Semiconductor Organization in the world
Location: Hyderabad
Skills Required
- 10-20 years of proven experience in Synthesis/STA
- Good understanding of overall design Flow RTL to GDS.
- Experience in signing off the full chip synthesis/STA for tape-outs
- Hands-on Experience in constraint generation and management for hierarchical designs.
- Detailed Understanding of DFT Constraints.
- Hand-on Synthesis & STA Experience on Lower Node Technologies with Synopsys/Cadence Tools.
- Hands-on Experience on Equivalent Checks with Synopsys / Cadence Tools.
- Good knowledge of Timing Budgets.
- Knowledge of Perl / TCL / Python scripting language
- Experience in multi-voltage designs using CPF/UPF.
- Good understanding of the Chip Interface Constraint Generation & Timing Closure.
- Hands-on experience in power analysis using PTPX
- Good understanding of VHDL / Verilog Constructs.
Responsibilities
- Responsible for Block/ Chip Tile Synthesis to achieve the best PPA.
- Constraint Generation & Maintenance for Block / SOC for sophisticated hierarchical Designs for all the Modes.
- Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts.
- Able to work on low-power & verify low-power intent with minimal direction.
- Responsible for Logical equivalence checks & Low Power Checks.
- Early RTL analysis for Clocking, Power, DFT coverage & suggestions to the Designer on the improvements.
- Support Verification team to enable GLS.
Contact:
Uday
Mulya technologies
Email : muday_bhaskar@yahoo.com
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