PD/STA/PV/Synthesis

2 months ago


Bengaluru, India UST Full time

Description : Synthesis

· Should be able to handle synthesis of SoC, tweak the flow to meet PPA targets

· Should be able to debug and resolve RTL2N LEC, N2N, LP-LEC issues

· Should be able to run CLP and resolve gate level CLP violations

· Familiarity with Multi-voltage, multi-power domain based Low power implementation

· Tools/Flows: Cadence: Genus, LEC, CLP

· Makefile based flow

· Tcl based automation

Description : STA

· Expected to handle constraints bring-up for Func/DFT modes

· Should have good constraints debugging skills

· Should be familiar with timing closure at various stages (preLayout, postLayout)

· Familiarity with Multi-voltage, multi-power domain based STA

· Tools/Flows: Cadence: Tempus

· Tcl based automation

· Makefile based flow

Description : PNR/PV

· Should be familiar with custom placement/routing using semi-automatic/manual method

· Should have worked on Physical Verification checks for Low Power SoC (DRC, ERC, LVS, ANT, ESD, DFM)

· Tools/Flows: Cadence: Innovus, Calibre

· Makefile based flow

· Tcl based automation

Description : PNR

· Should be able to handle P&R of SoC Blocks/Top

· Should be able to customize the PNR flow to meet PPA and low power requirements

· Should be able to resolve timing/congestion issues

· Should have worked on Multi-voltage, multi-power domain based designs

· Tools/Flows: Cadence: Innovus, Calibre, Tempus

· Makefile based flow

· Tcl based automation

Description : PNR/IR

· Should be able to handle power grid development using tool automation and custom scripts

· Should have handled SoC level EM/IR analysis (Static, Dynamic IR, power/signal EM) for SoC with power switches

· Should be able to analyse, root-cause and fix IRdrop issues

· Tools/Flows Cadence: Innovus, Redhawk-SC

· Makefile based flow

· Tcl based automation


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