Application Specific Integrated Circuit Design Engineer
4 days ago
ASIC Design Engineer
Location: Hyderabad
Experience: 5–10 years
Job Description
Key Responsibilities:
- Develop and implement RTL design for complex ASIC SoCs/IPs.
- Work on micro-architecture design, coding (Verilog/SystemVerilog), and RTL integration.
- Perform design synthesis, lint, CDC/RDC checks, and timing closure.
- Collaborate with verification, physical design, and architecture teams to ensure first-pass silicon success.
- Debug design issues at block and SoC level, support verification and post-silicon validation.
- Contribute to low-power, high-performance design techniques for advanced technology nodes.
Required Skills:
- Strong expertise in RTL design using Verilog/SystemVerilog.
- Hands-on experience with ASIC flow: synthesis, STA, constraints, ECO.
- Knowledge of standard protocols (AXI, AHB, PCIe, DDR, Ethernet, etc.).
- Familiarity with power intent (UPF/CPF) and clock/power domain crossings.
- Experience in working with EDA tools (Synopsys/Cadence/Mentor).
- Good problem-solving and debugging skills.
About Company
ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.
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Hyderabad, India ACL Digital Full timeASIC Design Engineer Location: Hyderabad Experience: 5–10 years Job Description Key Responsibilities: Develop and implement RTL design for complex ASIC So Cs/IPs . Work on micro-architecture design, coding ( Verilog/System Verilog ), and RTL integration . Perform design synthesis , lint , CDC/RDC checks, and timing closure. Collaborate...
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Hyderabad, India ACL Digital Full timeASIC Design Engineer Location: Hyderabad Experience: 5–10 years Job Description Key Responsibilities: Develop and implement RTL design for complex ASIC SoCs/IPs . Work on micro-architecture design, coding ( Verilog/SystemVerilog ), and RTL integration . Perform design synthesis , lint , CDC/RDC checks, and timing closure. Collaborate with verification,...
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Hyderabad, India ACL Digital Full timeASIC Design EngineerLocation: HyderabadExperience: 5–10 yearsJob DescriptionKey Responsibilities:Develop and implement RTL design for complex ASIC SoCs/IPs .Work on micro-architecture design, coding ( Verilog/SystemVerilog ), and RTL integration .Perform design synthesis , lint , CDC/RDC checks, and timing closure.Collaborate with verification,...
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Hyderabad, India ACL Digital Full timeASIC Design EngineerLocation: HyderabadExperience: 5–10 yearsJob DescriptionKey Responsibilities:- Develop and implement RTL design for complex ASIC SoCs/IPs.- Work on micro-architecture design, coding (Verilog/SystemVerilog), and RTL integration.- Perform design synthesis, lint, CDC/RDC checks, and timing closure.- Collaborate with verification, physical...
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Hyderabad, India ACL Digital Full timeASIC Design EngineerLocation: HyderabadExperience: 5–10 yearsJob DescriptionKey Responsibilities:Develop and implement RTL design for complex ASIC SoCs/IPs .Work on micro-architecture design, coding ( Verilog/SystemVerilog ), and RTL integration .Perform design synthesis , lint , CDC/RDC checks, and timing closure.Collaborate with verification,...
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Hyderabad, India ACL Digital Full timeASIC Design EngineerLocation: HyderabadExperience: 5–10 yearsJob DescriptionKey Responsibilities:- Develop and implement RTL design for complex ASIC SoCs/IPs.- Work on micro-architecture design, coding (Verilog/SystemVerilog), and RTL integration.- Perform design synthesis, lint, CDC/RDC checks, and timing closure.- Collaborate with verification, physical...
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hyderabad, India ACL Digital Full timeASIC/SOC Front End Design Engineer Job description: 1. Setup ASIC QA flows for RTL design quality checks. 2. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. 3. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. 4. Come up with clock constraints, false paths,...
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Hyderabad, India ACL Digital Full timeASIC Design Engineer Location: Hyderabad Experience: 5–10 years Job Description Key Responsibilities: Develop and implement RTL design for complex ASIC SoCs/IPs . Work on micro-architecture design, coding (Verilog/SystemVerilog ), and RTL integration . Perform design synthesis , lint , CDC/RDC checks, and timing closure. Collaborate with...
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Hyderabad, India ACL Digital Full timeASIC/SOC Front End Design EngineerJob description:1. Setup ASIC QA flows for RTL design quality checks.2. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains.3. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps.4. Come up with clock constraints, false paths,...
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Hyderabad, India ACL Digital Full timeASIC/SOC Front End Design Engineer Job description: 1. Setup ASIC QA flows for RTL design quality checks. 2. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. 3. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. 4. Come up with clock constraints, false paths,...
