IP Verification Engineering

4 weeks ago

Noida, India Hays Full time

This assignment is till 31st December 2024. (Extendable)

The work location is Noida/Bangalore.


Job Description:

Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering the first pass success of complex IPs using the latest advanced verification languages and methodology.

The person would be working with experienced and motivated team of Designers and Verification Leads and team to address the verification challenges in the context of the IP, SubSystem, and overall system, using simulation and formal verification and actively participate in supporting the debug at IP or SoC Level.

Key Responsibilities

• Drive (or participate in) the verification signoff using methodologies like SV UVM, assertions and formal verification to handle increasingly complex new or legacy IP/ SubSystem designs within aggressive, market-driven schedules.

• Own and ensure quality through coverage metrics driven approach and schedule adherence during all stages of the project cycle with respect to delivery milestone requirements.

• Carry out a thorough analysis of existing defects, change requests and new features and develop related Testbench components and execute Test plan for IPs/SubSystems.

• Target 100% Code Coverage (including exclusions), define and execute Functional Coverage through a mix of Random and directed tests, Cover bins, assertions.

• Shall be capable to own & perform the complete sign off process for the IP including 100% Code & Functional Coverage targets, Assertions, writing and updating test plans, Verification Guides, regression management etc.

• The Leads or solo owners are expected to work with minimal micro-management needs. He / She should be able to communicate with the Design and other verification project members to manage the task divisions and deliveries. He / She will also be responsible to deliver the weekly Status with desired metrics information.

Must Technical Skills

• Strong fundamental and expertise in UVM TB checkers, monitors etc.

• Expert in system Verilog & Verilog

• Strong hand on experience on AXB/AXI/APB interface protocol & debug

• Must have experience in end to end IP verification project cycle, including Testbench Strategies, TB development, simulation debugs.

• Verification simulator expertise from cadence ( irun/xrun ) or Synopsys (VCS ) tools

Key Technical Skills

• Self-starter with 4-12 years of relevant experience on IP / Sub-system verification on multimillion Gate and complex Design with multiple clocks with minimal supervision

• Desirable exposure to formal verification, assertions/SVA, functional coverage and regression management.

• Ability to debug Testbench and RTL issues and handle legacy Testbench and make enhancements.

• Experience desirable on at least one of the following:

o VC Formal (Synopsys), Jasper (Cadence)

o eManager / vManager (Cadence) or any other Regression Management Tool.

o Basic understanding of any Version Management and Ticketing tools.

Key Soft Skills

• Good communication skills.

• Hands on and ability to work well as part of a team both locally, and with remote or multi-site teams.

• Fast Learner and pro-active.

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