Director - HBM Memory Circuit Design Verification ( Hyderabad )

3 weeks ago

Greater Bengaluru Area, India Mulya Technologies Full time

Director - HBM Memory Circuit Design Verification

Top10 Semiconductor Organization in the world

Location: Hyderabad


As a Director/Senior Manager - HBM Memory Circuit Design Verification, you will work in a highly innovative, motivated, young, and dynamic design team capable of verifying complete products using state of the art memory technologies. You will need to have the ability to drive the team and the overall verification effort to ensure the timely delivery of a functionally correct design.


Responsibilities Will Include, But Are Not Limited To


  • Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes.
  • Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs.
  • Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features.
  • Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.
  • Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.
  • Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.
  • Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products and architectures.
  • Attract, recruit, train, engage and retain top talent to build a world-class verification team.

Successful Candidates For This Position Will Have


  • Familiarity with DRAM operation and JEDEC specifications, preferably with HBM product family
  • Extensive experience with CMOS circuit design and good understanding of semiconductor device physics
  • Knowledge and experience in digital (Verilog) and analog (FastSpice & Hspice) modeling and simulations
  • Experience in System Verilog, PLI coding.
  • Experience in UVM Test Bench
  • Experience in AMS verification and co-sim.
  • Good verbal and written communication skills with the ability to effectively synthesize and convey complex technical concepts to other partners and leadership.
  • Strong track record of innovation and problem-solving in high-performance memory development

Required Experience


  • B Tech or higher education
  • 15+ years of relevant Engineering experience



Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"

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