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Verification Lead

3 months ago

Greater Hyderabad Area, India Mulya Technologies Full time

Verification Lead

Top10 Semiconductor Organization in the World

Hyderabad


We are a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

About the job

Responsibilities

  • Perform functional verification, root cause design discrepancies, debug pre-silicon full chip designs and help resolve them.
  • Develop Test scenarios to increase the functional coverage for all DRAM and Emerging memory architectures and features.
  • Participate in development of advanced verification methodology for Emerging memory products.
  • Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.
  • Perform various checks to ensure accurate timing models.


Core Requirements

  • Good communication skills and ability to work well in a team.
  • Good in Verilog/SV/UVM concepts and verification
  • Deep understanding of fundamental digital design concepts and analytical capability in complex gate level circuit designs.
  • Well versed with SPICE and/or Verilog simulations and debug.
  • Substantial background in debugging designs as well as simulation environment.
  • Transistor level simulations to validate timing and internal margins would be a plus


Preferred Qualities

  • Experience in DRAM, SRAM or other memory related fields.
  • Experience in AMS verification and co-sim.
  • Good in verification approach, flow and concepts.


Job Description

  • Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.
  • Experience in deciphering circuit behavior from schematics.
  • Familiarity with circuit characterization, timing libraries - files and formats, timing arcs
  • Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.
  • Familiarity with static timing analysis
  • Hands-on experience in Gate level simulations with SDF back annotation.
  • Debug SDF annotation issues and ensure good annotation coverage.
  • Hands-on experience with latch based designs and their timing requirements.
  • Debugging Gate level simulation failures and root causing the failures to actual circuits.
  • Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.
  • Hands-on knowhow of System Verilog Assertions to specify expected design behavior
  • Familiarity with UVM is a plus
  • Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form.
  • Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor level - as applicable.


Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com