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Desing Verification Engineer

2 months ago

Bangalore Urban, India Cyient Full time

ASIC Engineer - DV

Job Description


  • 4 to 8yrs of experience in Design verification
  • Developed verification methodology and testplan for new design
  • Good knowledge on the verification flows, SV and UVM
  • Perform RTL code coverage and functional coverage, formal analysis
  • Be responsible for defining the verification strategy and plan for the development
  • Develop coverage-driven verification test plans
  • Knowledge on assertion development and coverage improvement
  • Write test specifications (plans) and create directed and random test cases


Mandatory Skills

Test Case Design,Functional Coverage,Coverage Driven Verification,Design Verification,Architectural Design,Perl Programming,Test Specifications,Test Planning,Universal Verification Methodology (UVM)