Staff/senior Staff AMS Verification Engineer
1 month ago
Job Description:
- Coding of simulation infrastructure using SystemVerilog & VerilogAMS
- Actively involved in all stages of product development including specification, circuit design, circuit modeling, verification, design for test, and silicon debug.
- Set up AMS verification environment, develop, and verify self-tested test benches for Mixed Signal chips and sub-circuits.
- Use and Development of Advanced mixed-signal simulation techniques to enhance simulation efficiency
- Generate Verification Plan from the Specifications using vManager
- Determine Coverage and design completeness requirements
- Work with Validation and Design to generate schematics or text based testbench
- Generate random-constraint tests to cover all customer-use-models
- Create Assertions, cover-groups, checkers, monitors and automatic reporting
- Set-up and run regression reports
- Works diligently to accomplish project goals and meet schedule requirements
Qualifications
- BSEE (MSEE pref.) or equivalent with 6+ years professional industry experience in AMS Verification engineering role
- Experience in digital and mixed-signal Verification
- VerilogAMS and Verilog/SystemVerilog languages, modelling, and AMS simulators
- UVM testbench creation, writing and implementation is a plus
- Proficient developing scripts (Shell, Perl, Python etc.), and Cadence SKILL language is plus
- Experience with AMS behavioural top-level modelling and verification methodology to speed up simulation (understanding accuracy/speed trade-off and interfaces)
- Must be able to work independently with limited supervision and work closely with the team.
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