ASIC RTL Design Engineer

6 days ago

Bengaluru, India 7hillsTS Full time

Key skills with hand on: ASIC,RTL Design, VLSI-SOC ,AMBA, Lint, CDC, Synopsys LintCDC/VerdiXcellium/Synopsys DC.

Experience: 5 - 25 years

Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune

Education: Engineering (excluding Mechanical/Civil)


Detailed JD:

IP RTL design targeted for SOC, Static checks, some basic protocols

Expertise in SoC subsystem/IP design

Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog

In depth knowledge on RTL quality checks (Lint, CDC)

Knowledge of synthesis and low power is a plus

Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)

Good understanding of timing concepts

Knowledge of one or more of the interface protocols

PCIe/DDR/Ethernet/I2C,UART/SPI

Expertise in setting up and using tools like

  1. Spyglass Lint/CDC
  2. Synopsys DC
  3. Verdi/Xcellium

Understanding of scripting languages like Make flow, Perl ,shell, python etc

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