ASIC/FPGA Verification Engineer

1 month ago

Gurugram, India Ciena India Private Limited Unitech Full time

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

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Why Ciena:

We are big proponents of life-work integration and provide the flexibility and tools to make it a reality with remote work and potentially, part-time work. We believe an inclusive, diverse and barrier-free work environment makes for empowered and committed employees. We recognize the importance of well-being and offer programs and benefits to support and sustain the mental and physical health of our employees and their families and also offer a variety of paid family leave programs. We are committed to employee development , offering tuition reimbursement and a variety of in-house learning and mentorship opportunities. We know that financial security is important. We offer competitive salaries and incentive programs, RSU’s (job level specific) and an employee share option purchase program. We realize time away to recharge is non-negotiable. We offer flexible paid time off Great work deserves recognition. We have a robust recognition program, with ongoing and enhanced awards for exemplary performance.

How You Will Contribute:

This position is for an experienced FPGA Verification engineer for supporting FPGA development Programs for Packet Networking hardware.

 The successful candidate will carry on chip level verification activities and support lab validation of FPGAs, for a variety of FPGA designs, and will be responsible for (but not limited to) the following:

Establish verification and design of testbench architecture, and infrastructure. Work with the design team to establish test priorities. Create verification plan. Create and executing testcases. Debug of failing testcases to point issues in design as bugs or refinements. Simulations driving bug finding and fixing activities. Collaborate with peers and mentor junior verification engineers. Running regressions and keeping verification testbench and testcases up to date with design in source code maintenance system like Perforce, other tools. Support lab validation of bugs and issues based on Verification to see them resolved in lab.

What Does Ciena Expect of You?

Initiative – you’re a self-starter who works with limited direction and is committed to delivering against aggressive deadlines. Agility – you are readily able to make key decisions and manage competing and ever-changing account priorities and largely driven by the software development process. Communication expertise – you have the ability to influence and tailor your message and ideas to the audience to ensure understanding and consensus. The flexibility to  work independently  and as  part of a broader team – you thrive in a multi-disciplinary team environment, but are comfortable working independently as required. Relationship builder – with an ability to influence, you’re able to get work done through others. A commitment to innovation – you keep abreast of the market and competitive developments and are always keen to formulate new ideas and problem solve.

The Must Haves:

Bachelor’s degree in engineering or equivalent in Electronics or Electronics and Communication. Experience working as a FPGA/ASIC Verification Engineer for 1+ years. Experience in developing testbench environments and testcases using System Verilog and UVM. Good coding skills in System Verilog for Verification including class based testbench construction with drivers, monitors , scoreboard, assertions and other testbench areas. Experience with both directed and constrained-random stimulus generation and testcase writing. Good problem solving and debugging skills using simulator-based waveform debug tools. Skills for bug finding using simulations. Understanding RTL design code in Verilog/System Verilog. Experience with one of Cadence Xcelium simulation tools or other simulation tools like Mentor Graphics Questa or Synopsys VCS verification tools or FPGA simulator tools. Knowledge of protocols such as I2C, SPI , AXI , AHB or other protocols shall be added plus. Working knowledge of Linux operating systems and editors like vi , gvim etc.

Assets:

Independent self-starter who can work with minimum guidance. Strong commitment to product excellence with bug finding and root causing via extensive waveform-based debug. Good communications skills Collaboration with stakeholders in Board and Software teams besides FPGA team.Strong analysis, coding, testing, and documentation skills.Ability to resolve complex issues that may require detailed design debug.Position requires proficient troubleshooting and problem-solving skills.Big finding and resolution via testcase based debug.Strong commitment to product excellence and quality. Not ready to apply? Join ourto get relevant job alerts straight to your inbox.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an   Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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