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FPGA Verification Engineer
2 months ago
Key Responsibilities:
FPGA Verification Engineer with SystemVerilog and UVM experience to verify FPGA designs used in semiconductor plasma etchers.
Must own and drive requirements, design, and implementation of verification solutions including modeling DSP, creating and modifying UVM modes and test infrastructure.
Model signal processing path and algorithms in MATLAB and port them to the verification environment and work with MATLAB models to create simulation stimulus.
Skillset Requirements:
Typical 6+ years of experience in UVM based verification of FPGAs and/or ASIC and specifically, Xilinx SoC devices. [Minimum 5, Max of 10 years]
BS or MS Degree in Electrical Engineering or Computer Science.
Prefer experience working on Xilinx Zynq based systems and interfacing with an application running on an RTOS at the application layer.
Knowledge of digital signal processing: FFT, FIR, IIR. Must be well versed in communications protocols (SPI, I2C, EtherCAT, Ethernet, RS232).
The position requires excellent soft skills to be part of a cross functional team, excellent written & oral communication and presentation skills.
FPGA Toolset
FPGA build: Vivado System Edition
Simulation: Questa with UVM support
Additional Skills
Design, setup, and write software to control lab test setups for FPGA validation.
Validate FPGA RTL blocks with unit level testbenches.
Proficient in scripting languages for building, simulating and running FPGA based designs.
Communicate with written documentation including block, timing and finite state diagrams.
