Physical Verification Engineer

4 weeks ago

Bengaluru, India Digicomm Semiconductor Pvt. Ltd. Full time
JobdescriptionExciting Opportunity for PhysicalVerification Engineers Elevate your career with DigicommSemiconductor Private Limited and take the next leap in yourprofessional journey. Join us for unparalleled growth anddevelopment.
Responsibilities:
  • DesignRule Checking (DRC): Run DRC checks using industrystandard tools toidentify violations of manufacturing design rules. Collaborate withlayout designers to resolve DRC issues.
  • Layoutvs. Schematic (LVS) Verification: Perform LVS checks to ensure thatthe physical layout accurately matches the schematic and that thereare no electrical connectivitydiscrepancies.
  • Electrical Rule Checking (ERC):Verify that the layout adheres to electrical constraints andrequirements such as voltage and current limitations ensuring thatthe IC functions as intended.
  • Design forManufacturing (DFM): Collaborate with design and manufacturingteams to optimize the layout for the semiconductor fabricationprocess. Address lithography and process variationconcerns.
  • Process Technology Calibration:Calibrate layout extraction tools and parameters to match thespecific process technology used forfabrication.
  • Resolution Enhancement Techniques(RET): Implement RET techniques to improve the printability oflayout patterns during the photolithographyprocess.
  • Fill Insertion: Insert fill cells intothe layout to improve planarity and reduce manufacturingrelatedissues such as wafer warping andstress.
  • MultiPatterning and Advanced Nodes:Deal with challenges specific to advanced process nodes includingmultipatterning coloring and metal stackvariations.
  • Hotspot Analysis: Identify andaddress potential hotspot areas that may lead to manufacturingdefects or yield issues.
  • PostProcessingSimulation: Perform postprocessing simulations to verify that thelayout is compatible with the manufacturing process and does notintroduce unwanted parasitics.
  • ProcessIntegration Checks: Collaborate with process integration teams toensure the smooth integration of the design with the semiconductorfabrication process.
  • Documentation: Maintaindetailed documentation of verification processes methodologies andresults.

Qualifications:BTECH/MTECH
Experience:2 to 5 years of Experience

layout,semiconductor,physicalverification

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