Principal Engineer
6 months ago
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
JR50039 Principal Engineer - ASIC Architect Seeking an ASIC Architect/micro-Architect for Micron’s ASIC architecture team.
Architect should have solid understanding and experience with RTL design (IP, SoC) DV (Coverage concepts) and implementation flow –(synthesis, P&R, STA, DFT, power-islands, floor-planning, CTS, IR-drop) – and deep understanding of how architecture decisions impact these flows.
Architect will be responsible for developing, contributing, and leading ASIC macro and micro-architecture activities for Micron’s leading edge ASIC storage controllers.
Candidate should be highly motivated with strong communication skills, attention to detail, and quality oriented.
Responsibilities include, but not limited to:
Reviewing product, System and FW requirements Collaborate with ASIC architects and system architects to define and document the feature sets and data/control flows implemented by the controller and each of its component IPs. Defining requirements for ASIC design, verification, and physical implementation teams. Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions. Reviewing and configuring 3rd party IPs. Supporting other teams in the ASIC organization and reviewing their work Supporting product teams with documentation, code-reviews, and silicon debug Continuously finding opportunities for improving design quality and design practicesMinimum Qualifications:
10+ years of ASIC experience RTL design experience in Verilog/System Verilog Knowledge and experience in various aspects of SOC design, verification, and implementation flows Experience with low-power design techniques Scripting and Unix shell language experience: Perl, Python, Unix shell scripts Ability to read and understand SW code Understanding of CPU and memory architectures, data path pipelining mechanisms, distributed system design, ASIC low-power implementations, clock and reset methodologiesPreferred Skills:
Knowledge of PCIe + CXL is an advantage Design/Architecture experience with high-speed serial and parallel interfaces ( PCIe/UCIe, DDR, LPDDR) Design/Architecture experience with CHI, Coherency, Memory Controller, Fabric/NoC Experience with HW modeling languages Familiarity with Security and RAS design is an advantageEducation :
, BS/BE (Electronics)-
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