PD full chip leads
3 weeks ago
We are hiring PD full chip leads for Bangalore location.
KEY RESPONSIBILITIES:
Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF
Full chip Hierarchical planning, block planning, block level constraints, hierarchical clock tree implementation, block integration and chip finishing.
Full chip/Sub system level Clock tree synthesis and advanced clock tree implementation.
Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion and logic equivalence
Low power design with power estimation/optimization, including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption.
PPA (Power, Performance, Area and Schedule) closure and flow development for key IPs
Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for a SOC
Experience in 5nm, and 16nm technologies.
PREFERRED EXPERIENCE:
12-20 years of relevant work experience.
Expertise in Design/Fusion Compiler Physical Design flows/methodologies or equivalent tools.
Expertise in Signoff tools like Primetime for Timing
Should have worked as a go to person or technical lead for at least few full chip projects.
Strong inter-personal skills and ability to collaborate with teams spread across multiple geos.
Should have good scripting experience in Shell, Python, Perl, TCL, UNIX, along with decode/debug old existing scripts.
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