Staff Engineer, Design Verification
3 weeks ago
Analog Devices is a leading global high-performance analog technology company dedicated to solving the toughest engineering challenges. We enable our customers to interpret the world around us by intelligently bridging the physical and digital with unmatched technologies that sense, measure, power, connect and interpret. The APW group within AES focuses on developing a wide variety of Power Management IC’s and systems which target virtually every critical system within a modern vehicle.
In this role, you will lead a Verification team ensuring bug-free operation of sophisticated mixed-signal system-on-chip (SoC) integrated circuits for smart power systems, and you will also manage the verification of numerous standard power products including Buck, Boost and Buck-Boost topologies as well as unique high voltage solutions.
Responsibilities:
Hiring and managing a team of Verification Engineers for a wide variety of Automotive Power products Verification of complex mixed signal designs and sub-systems using leading edge verification methodologies. Architecting a unified verification testbench environment supporting both digital only and mixed signal verification requirements (UVM based) Defining test plans, tests and verification methodology for block / chip-level verification. Working with the design team in generating test-plans and closure of code and functional coverage Continuous interaction with analog mixed signal and firmware teams Tracking and management of design verification improvements Technically mentoring less-experienced verification engineers on SoC Verification. Mentor Junior Engineers
Minimum qualifications:
Preferred Qualifications:
Mixed-signal simulation (Cadence AMS), interfacing with analog functions Experience with writing Verilog-AMS and Real Number Models for Analog Functions Leadership skills enabling one to define, sell and implement a verification strategy Demonstrated ability to communicate with peers, managers, and project stakeholders effectively using both verbal and written communications. Proficient in developing unit and SoC level test benches using UVM Behavioral modeling of analog blocks, System Verilog Real-Number Modeling, behavioral model validation and mixed-signal simulators like Cadence Xcelium Working with PMIC product Gate Level Simulation (GLS) verification flow for SoC verification. Pre and post-silicon verification test flow including HW, SW and FW Verilog, C/C++, System C, Java, TCL/Perl/Python/shell-scripting RTL design/front-end design/FPGA flow experience Good knowledge all aspects of the RTL2GDS flow Low power methodologies such as CPF/UPF Some experience with Functional Safety requirements Versatile in communication protocols such as I2C and SPI, 1-wire Knowledge/verification of custom digital interfaces (I2C, SPI, UART, etc.). Strong interpersonal and teamwork skills with demonstrated ability to build and motivate a team Self-motivated and enthusiastic Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days-
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