Principal Engineer, PHYSICAL DESIGN

5 months ago

Bengaluru, India Onsemi Full time

OnSemi is seeking a Principal Physical Design Engg, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following: 

P&R Lead with hands on experience in P&R, power planning, floor planning, clock tree building, congestion analysis for complex multi power domain designs Strong in problem solving with deep understanding of technical issues. Candidate should have keen eye to improve existing flow and methods with positive impact on PPA.  The ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status Good understanding of IR & power analysis and hands on experience in using related tools/flows Solid understanding of Verilog, TCL and Perl/Python programming languages BS in Electrical Engineering or related + 8 years of experience, or MS + 7 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments Solid understanding of RTL design, ASIC synthesis, timing analysis and CDC, P&R, UPF Solid understanding of Verilog, TCL and Perl/Python/XML programming languages Solid track record of releasing complex ICs to market  Ability to clearly articulate issues, challenges, and concerns to all levels of management  Must have good written and verbal cross-functional communication skills BS in Electrical Engineering or related + 8 years of experience, or MS + 7 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments Solid understanding of RTL design, ASIC synthesis, timing analysis and CDC, P&R, UPF Solid understanding of Verilog, TCL and Perl/Python/XML programming languages Solid track record of releasing complex ICs to market  Ability to clearly articulate issues, challenges, and concerns to all levels of management  Must have good written and verbal cross-functional communication skills

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