FPGA RTL Design Engineer
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Experience:
8 to 15 Years Job
Location:
India Job Summary: We are looking for an experienced FPGA RTL Design Engineer with strong expertise in VHDL and high-speed packet processing. The candidate will work on advanced 5G/wireless communication products and develop high-performance FPGA-based solutions.
Key Responsibilities
Understand packet processing requirements from system architects Design FPGA RTL architecture and microarchitecture Develop and implement RTL using VHDL Perform functional verification, linting, synthesis, and timing closure Validate FPGA designs and optimize performance Work with verification and firmware teams for integration Support board bring-up and debugging activities Optimize designs for power, performance, and area (PPA) Required
Skills:
Strong experience in FPGA RTL design using VHDL Experience in high-speed packet processing Good understanding of FPGA design flow Knowledge of synthesis, STA, and timing closure Strong debugging and problem-solving skills Experience in wireless communication or 5G domain is preferred Exposure to Altera Agilex or AMD Zynq RFSoC is an advantage Knowledge of DSP fundamentals and protocols like 5G, LTE, Wi-Fi is a plus Familiarity with UVM/System Verilog is preferred
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