Principal IP/RTL Design Engineer for Ethernet Switch

15 hours ago

Greater Hyderabad Area, India Mulya Technologies Full time ₹ 1,04,000 - ₹ 1,30,878 per year

Principal IP/RTL Design Engineer for Ethernet Switch

Hyderabad / Bangalore

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore

Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market.

IP/RTL Design Engineer for Ethernet Switch

Position Overview

We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads.

Key Responsibilities

  • Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches.
  • Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals.
  • Optimize designs for low latency, high throughput, and power efficiency.
  • Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control.
  • Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation.
  • Use P4 or related languages for programmable packet processing.
  • Collaborate with teams for synthesis, timing closure, and IP integration.
  • Document designs and stay updated on AI networking trends.

Required Qualifications

  • Education: BS/MS/PhD in Electrical or Computer Engineering.
  • Technical Skills:
  • Proficient in Verilog/SystemVerilog for design.
  • Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control.
  • Experience with InfiniBand, NVLink, or similar protocols.
  • Proficiency in P4 or programmable data plane languages.
  • Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE.
  • Familiarity with power optimization or SDN.
  • Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools.
  • Soft Skills: Strong problem-solving, communication, and teamwork skills.

Contact:

Uday

Mulya Technologies

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