Principal ASIC Digital Design Engineer- IP Development

Job Description

Category: Engineering
Hire Type: Employee
Job ID: 13120
Remote Eligible: No
Date Posted: 29/10/2025

Job Title: Principal ASIC Digital Design Engineer We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly experienced digital design professional with a strong track record in architecting and implementing complex RTL-based IP Cores. With a deep passion for solving intricate technical challenges, you bring over 15 years of hands-on experience in ASIC design and development, specifically within the context of high-performance, low-power, and robust system-on-chip (SoC) solutions. You thrive in dynamic, globally distributed teams, and you're motivated by the opportunity to work on next-generation technologies that enable breakthroughs in AI, machine learning, automotive, and cloud infrastructure. You are detail-oriented and methodical, with the ability to translate high-level requirements into precise micro-architectures and design specifications. Your expertise spans multiple industry-standard protocols (such as DDR, PCIe, AMBA, Ethernet, USB, and MIPI), and you are adept at leveraging industry-leading EDA tools for simulation, synthesis, and formal verification. You are proactive, capable of working independently, and always seeking opportunities to innovate and drive technical excellence. Your communication skills enable you to collaborate effectively with cross-functional teams, mentor junior engineers, and articulate complex technical concepts clearly. With a growth mindset, you are eager to continue expanding your skills in safety standards, design automation, and emerging technologies.

What You'll Be Doing:

• Translating standards and functional specifications into detailed architecture and microarchitecture specifications for advanced digital IP Cores.
• Making critical architectural decisions and leading the development of complex RTL designs from concept through implementation.
• Collaborating with verification teams to define and refine verification plans, and supporting the creation of robust test strategies.
• Writing high-quality Verilog/System Verilog code and using simulation tools to validate design functionality and performance.
• Driving synthesis, static timing analysis, lint, and CDC/formal checking flows to ensure design quality and compliance with stringent requirements.
• Providing technical leadership and mentoring to other team members, fostering a culture of continuous learning and innovation.
• Engaging with cross-site, international teams to deliver IP solutions optimized for server, AI/ML, automotive, and other end-customer applications.

The Impact You Will Have:

• Enable Synopsys' customers to accelerate time-to-market with differentiated, high-performance SoC solutions.
• Contribute to the world's broadest portfolio of silicon IP, supporting a wide range of applications from cloud servers to autonomous vehicles.
• Raise the bar for design quality and reliability by implementing industry best practices in verification, synthesis, and safety.
• Drive innovation in digital design methodologies and IP core architectures, influencing the direction of future product development.
• Mentor and upskill team members, cultivating technical excellence and collaborative problem-solving within the team.
• Play a key role in Synopsys' global Solutions Group, delivering complex IPs that power next-generation technologies.

What You'll Need:

• Bachelor's or Master's degree in Electrical/Electronics Engineering, with 15 years of relevant experience in ASIC digital design.
• Deep knowledge of one or more protocols: DDR, PCIe, AMBA (AMBA2, AXI, CHI), SD/eMMC, Ethernet, USB, MIPI.
• Hands-on expertise in Verilog/System Verilog coding, simulation, and advanced EDA tools.
• Strong proficiency in synthesis flow, static timing analysis, lint, CDC, and formal checking methodologies.
• Experience in developing micro-architecture and detailed design from functional specifications.
• Familiarity with scripting languages (C/C , TCL, Perl, Python) is a plus.
• Understanding of functional safety standards (ISO26262, FMEDA) and prior exposure to SVA/formal verification tools is advantageous.

Who You Are:

• A proactive self-starter with a passion for technical innovation and solving challenging design problems.
• Detail-oriented, precise, and committed to delivering high-quality, robust solutions.
• Effective communicator, able to collaborate across geographies and functions.
• Team player who enjoys mentoring and knowledge sharing.
• Comfortable working independently and making informed architectural decisions.
• Adaptable and eager to learn new technologies and methodologies.

The Team You'll Be A Part Of:

You will join the Solutions Group at our Bangalore Design Center, a collaborative and innovative team focused on developing industry-leading RTL-based IP Cores. The team works closely with architects, designers, and verification experts worldwide, delivering IP for a diverse set of high-impact applications. Our culture emphasizes technical excellence, continuous learning, and cross-functional teamwork to empower each member to contribute meaningfully to Synopsys' mission.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Locations: Bengaluru, Karnataka, India

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