Memory Design Lead Engineer

1 day ago

All India ACL Digital Full time ₹ 12,00,000 - ₹ 36,00,000 per year
As a Senior Memory Design Lead Engineer based in Bangalore, your role involves developing memory compilers and memory Fast Cache instances for next-generation Cores, focusing on achieving outstanding Power, Performance, and Area (PPA). You should have a solid understanding of computer architecture and concepts, basic knowledge of CMOS transistors and their behaviors, proficiency in high-speed/low-power CMOS circuit design, clocking schemes, static and complex logic circuits, and evaluating trade-offs between Power, Performance, and Area in typical CMOS design. An engineering demeanor, passion for circuit design, and good interpersonal skills are crucial. **Key Responsibilities:** - Develop memory compilers and memory Fast Cache instances for next-generation Cores - Focus on achieving outstanding Power, Performance, and Area (PPA) - Understand computer architecture and concepts - Utilize basic knowledge of CMOS transistors and their behaviors - Proficient in high-speed/low-power CMOS circuit design - Implement clocking schemes, static and complex logic circuits - Evaluate trade-offs between Power, Performance, and Area in typical CMOS design - Ensure SRAM/memory design Margin, Char, and related quality checks - Utilize scripting languages like Perl, TCL, or Python - Work on Cadence or Synopsys flows - Expertise in circuit simulation and optimization of standard cells **Qualifications Required:** - Minimum 8+ years of experience in SRAM/memory design Margin, Char, and related quality checks - Familiarity with scripting languages such as Perl, TCL, or Python - Experience working on Cadence or Synopsys flows - Expertise in circuit simulation and optimization of standard cells Feel free to apply or share/refere profiles by contacting hidden_email for this exciting opportunity.,

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