Principal Emulation Engineer

2 days ago

Bengaluru, Karnataka, India Astera Labs Full time ₹ 20,00,000 - ₹ 25,00,000 per year

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at

We are seeking experienced Emulation Engineers with a strong aptitude for working on Emulation Platforms. Candidates should have a deep understanding of system-level aspects of ASIC development and be skilled in emulation testbench and test plan development. 

Responsibilities: 

Develop and execute emulation test benches and test plans. Utilize coding and problem-solving skills to contribute to the functional verification of designs. Manage the full life cycle of emulation, from planning to system-level tests. Develop platform agnostic methodologies that scale across traditional DV and emulation and post-silicon bringup for functionality, performance etc. Collaborate with software and system validation teams to develop and execute test plans on emulation platforms. 

Basic Qualifications: 

Strong academic background in Electrical Engineering (Bachelor's required, Master's preferred). Minimum of 10 years' experience in verifying and validating complex SoCs for server, storage, and networking applications. Proficiency with industry-standard simulators, revision control systems, and regression systems. Professional attitude with the ability to prioritize tasks and work independently with minimal supervision. Entrepreneurial, open-minded attitude with a customer-focused mindset.  

Required Experience: 

Full verification lifecycle experience on ASICs. Proven ability to deploy hybrid techniques, including directed and constrained random testing. Experience in stress testing at the system level for bug identification. Ability to independently develop test plans and test sequences, generate stimuli, and collaborate with RTL designers to debug failures. Skill in identifying and writing test cases using a combination of C and System Verilog constructs to cover functional and code coverage of ASICs. 

Preferred Experience: 

Proficiency in scripting tools (Perl/Python) for automating verification infrastructure. Experience with System Verilog/UVM/C/C++/SystemC Experience with transactors from third-party vendors and communication protocols such as PCI-Express (Gen-3 and above), Ethernet, DDR4/5, NVMe, etc. Familiarity with SystemC-based verification and modeling strategies. 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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