CPU Staff Physical Design Engineer

3 days ago

Noida, Uttar Pradesh, India Qualcomm Full time ₹ 5,00,000 - ₹ 8,00,000 per year

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing].

We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.

We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

Desired experience:

  • 8+ years of experience in Physical design, STA.
  • Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk].
  • Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect.
  • Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs.
  • Should be aware about the tricks for minimizing power.
  • Experience in deep submicron process technology nodes is strongly preferred.
  • Knowledge of high performance and low power implementation methods is preferred.
  • Willing to push PPA to the best possible extent.
  • Strong fundamentals.
  • Expertise in Perl, TCL language

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