RTL Design(GPU)

16 hours ago


Bengaluru, Karnataka, India Qualcomm Full time ₹ 5,00,000 - ₹ 8,00,000 per year

Job Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Minimum 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV

Experience in Logic design/micro-architecture/RTL coding is a must.

Must have hands on experience with design and integration of complex multi clock domain blocks

Experience in Verilog/System-Verilog is a must.

Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture

Hands on experience in Multi Clock designs, Asynchronous interface is a must.

Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.

Work closely with the Design verification and validation teams for pre/post Silicon debug

Hands on experience in Low power design is preferable

Experience in Synthesis / Understanding of timing concepts for ASIC is must

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.


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