FPGA IP Verification Manager

Job Details
Job Description:
Team Leadership And Management

• Lead and mentor a team of engineers working on FPGA IP verification
• Define team priorities, set goals, and monitor performance through KPIs and regular performance reviews.
• Foster an environment of learning, collaboration, and technical excellence to drive verification efficiencies.

Technical Management

• Oversee the development and delivery of verification of IPs owned by the team and ensure alignment with QPDS/ releases.
• Drive innovation in verification methodologies to improve quality & efficiency.
• Collaborate with FPGA design, software, and validation teams to help integrate IP into the Quartus ecosystem.
• Ensure robust quality for the IP owned.
• Provide technical guidance on verification methodology.

Functional Expertise

• Hands-on technical verification manager who will own the verification on IPs for FPGA.
• Performs functional logic verification of an FPGA to ensure the design will meet specification requirements. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
• Executes verification plans and defines and runs simulation models to verify the FPGA design and uncover bugs.
• Replicates, root causes, and debugs issues in the pre-silicon environment.
• Finds and implements corrective measures to resolve failing tests.
• Collaborates with FPGA architects, RTL developers, and software teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
• Maintains and improves existing functional verification infrastructure and methodology.
• Documents, reviews, and executes the verification strategy plan on different methodologies/techniques used to enable feature coverage as per the microarchitecture specifications.
• Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.
• Complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).

Project Management

• Develop and maintain project timelines, resource planning, and deliverables, ensuring timely execution.
• Proactively identify risks and bottlenecks, develop mitigation strategies, and communicate updates to stakeholders.

Qualifications
Education:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Experience

• 15+ years of experience in verification in IP/ FPGA/ SoC/ ASIC.
• 3+ years of experience in managing technical teams, mentoring engineers, and driving performance.
• Proven expertise in RTL design and verification for FPGA architectures.
• Hands-on experience with OVM/UVM, System Verilog, and constrained random verification methodologies.
• Strong background in simulation tools such as ModelSim, Questa, VCS, or similar EDA simulators.
• Experience with Ethernet/ PCIe/ PIPE & FPGA architecture is an added advantage.
• Experience in design verification with developing, maintaining, and executing complex IPs and/or SOCs.

Leadership & Soft Skills

• Proven ability to lead and develop technical teams, drive collaboration, and deliver results.
• Strong problem-solving and analytical skills with a proactive mindset.
• Excellent communication and stakeholder management skills, capable of engaging both technical and non-technical audiences.

Job Type
Regular

Shift
Shift 1 (India)

Primary Location:
Ecospace 1

Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.