Principal Engineer

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Job Description:

You will be working with our DFT team in Hyderabad to develop DFT tests. These tests are intended to catch manufacturing defects in targeted IPs inside FPGA/SoC. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures, ATPG, MBIST Verification at full chip level, DFT/Testability hooks in Silicon, methods and principles to develop ATPG/Functional test vectors, simulate, debug and generate patterns for production tests.

You will work closely with Architects, Design engineers, Verification engineers and Software engineers across the globe to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required.

Requirements/Qualifications:

Required Skills and Experience

• Understanding basics of DFT structures (OCC, SSN, SIB, WBRs, compression engine), ATPG(Intest/Extest) , MBIST, Boundary Scan (IEEE Tap Controller,

Generating, verifying and debugging test patterns at block and chip-level retargeting to test the designs and firmware for new FPGA families.

• Improving, extending and porting existing manufacturing test designs to all FPGA family members.

• Test specification, plan, and documentation
• BS or MS in EE with 5 to 6 years of experience of working in DFT

• Hands on experience with industry standard ATPG tools, MBIST, pattern simulation and debugging skills at block and chip-level.

• Hands-on experience with Verilog behavioral RTL and Gate level netlist.

• Comfortable with Unix, Perl and/or Shell scripting and familiar with Revision Control (CVS, SVN, …)

• Strong analytical and problem-solving skills

• Excellent communication, documentation and presentation skills.

• Must have strong self-learning ability and enjoy working in teams spread across globe.

• Good programming skill/Firmware development skills with C, C++/assembly will be a big plus.

• Exposure to ASIC/FPGA design flow and methodology is a plus (HDL, synthesis, static timing analysis, constraining, Place & Route)

Education and Qualifications

• 7-8 years of professional experience in digital design and DFT
• Bachelor of Engineering with Diploma in VLSI /Master of Science / Engineering Degree.

Travel Time:

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